Silicon Nanowires and Silicon/molecular Interfaces for Nanoscale Electronics

of the thesis The thesis describes the realization of high-performance silicon nanowire (Si NW) logic circuits and a novel surface modification technique for nanoscale electronics applications. First, doped Si NWs were generated via the superlattice nanowire pattern transfer (SNAP) process, forming aligned, uniform, ultra-dense NW arrays. The NWs served as the channel material for field-effect transistors. NWs could be doped nor ptype using a diffusion doping process and both n-FETs and p-FETs could be fabricated simultaneously on the same substrate. Individual p-FETs exhibited excellent performance metrics compared to other NW and carbon nanotube (CNT) transistors, including high on/off ratios, low off currents, high mobilities, and low subthreshold swings. The n-type devices also had good characteristics, although they did not perform as well as the p-FETs. A comparison of nanowire and microwire device performance revealed that the NW FET performance was dominated by the high surface-area-to-volume ratio. These devices were integrated into complementary symmetry (CS) inverter circuits, which showed a consistent performance and a gain (a measure of performance) of ~ 5. Circuit performance was optimized by utilizing a methodology that combined prototype devices with circuit simulations. First, prototype devices were fabricated and their DC and AC characteristics were tabulated into a look-up-table model. This model was accessed by a circuit simulator, which could predict the performance of arbitrary circuits utilizing these devices and provide feedback into the device design. Circuits could then be fabricated from the optimized devices resulting in increased performance.